MIMOSA 3 and 4

MIMOSA 3 (top) and MIMOSA 4 (bottom)

MIMOSA 3:

fabricated by IBM in Spring 2001
0.25 µm CMOS technology
epitaxial layer thickness: 2.5 µm
nominal power supply: 2.5 V
2 arrays of 128 x 128 pixels
pixel size: 8 x 8 µm²
gate oxide thickness: 5.84 nm
diode (n-well/p-substrate) size:
1 x 1 µm² - 2.1 fF
serial analogue read-out
max. clock frequency: 40 MHz
radiation tolerant transistor design
low noise (6 e^- ENC)
structures for radiation hardness tests

MIMOSA 4:

fabricated by AMS in Spring 2001
0.35 µm commercial CMOS process
nominal power supply: 3.3 V
gate oxide thickness: 7.5 nm
no epitaxial layer
4 arrays of 64 x 64 pixels
pixel size: 20 x 20 µm²
diode (n-well/p-substrate) size:
2 x 2 µm² - 1.8 fF
serial analogue read-out
max. clock frequency: 20 MHz
radiation tolerant transistor design

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